# Project Simulation

Before programming the FPGA, simulate the circuit behavior:

1\. Go to the “**Simulate**” tab.

2\. Click “**Advanced Simulation**”.

3\. In advanced mode, go to **Menu > Run Iverilog**.

4\. **Check for messages:**

- - No errors → you're ready for synthesis.
    - Errors → review the block connections and run the simulation again.

**![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXeJwYMJXCNkgyqJ3A_7VvI8nzhZnmj0DF8fjBK21XMl407TpuWTE_6GVN-bMo1pkbv2LGupdnvphguVTN0aPi8YlgOCMfVBFV_85e-h9TLs7y5cMEq8CDbeIMQCi2g_9N79MXUnYVqTCHTZWOkbkdQ?key=ka9cvOfjRP6vEgqiQGaEnLpk)**

  
During simulation, observe the following signals:

<div align="left" dir="ltr" id="bkmrk-signal-description-c"><table border="1" class="align-center" style="width: 78.2143%; border-collapse: collapse;"><colgroup><col style="width: 24.154%;" width="101"></col><col style="width: 75.8202%;" width="317"></col></colgroup><thead><tr><td class="align-center">Signal

</td><td class="align-center">Description

</td></tr></thead><tbody><tr><td class="align-center">counter\[7:0\]

</td><td class="align-center">Should increment with each 20 Hz clock pulse.

</td></tr><tr><td class="align-center">pwm

</td><td class="align-center">PWM signal with increasing duty cycle.

</td></tr><tr><td class="align-center">led0

</td><td class="align-center">Inverted PWM signal applied to the LED.

</td></tr></tbody></table>

</div>