# SPI Protocol

# SPI Protocol Overview

SPI (Serial Peripheral Interface) is a synchronous, full-duplex communication protocol used for high-speed data exchange over short distances. It follows a master–slave architecture with four primary signals:

- **SCLK (Serial Clock):** Clock signal generated by the master to synchronize data transfers.
- **MOSI (Master Out Slave In):** Data line from master to slave.
- **MISO (Master In Slave Out)**: Data line from slave to master.
- **CS\_n (Chip Select, active-low):** Signal used by the master to select the slave device.

Bits are shifted out on MOSI and shifted in on MISO on each clock edge, according to the configured clock polarity (CPOL) and phase (CPHA).

**![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXe-uEbDHG7-vJgaabPgYQI1FqSRE0h_BMew38jst8ixSUM1xpOhnhsXhTcPy_GHjQmGMx8ns5tn590eWGMCUi2nCF3LkMCoDCyGdgvuclifiUMeTsz8N5OYqzBOE-V-iGYnhTLh8FuABUU6we-wWg?key=jf2tbarAhI5qOMz-WeYmBR_q)**

# Creating the Project in ChipInventor

1\. Open ChipInventor.

2\. Click New Project.

3\. Fill in the fields:

- Name: SPI Communication Tutorial
- Description: SPI Master–Slave Data Transfer with LED Display
- Type: FPGA

4\. Click Create.

# Blocks Used

<div align="left" dir="ltr" id="bkmrk-block-function-spi_m"><table border="1" class="align-center" style="border-collapse: collapse;"><colgroup><col width="108"></col><col width="442"></col></colgroup><thead><tr><td>Block

</td><td>Function

</td></tr></thead><tbody><tr><td>spi\_master

</td><td>Generates SCLK, MOSI, and CS\_n; sends incremental byte values

</td></tr><tr><td>spi\_slave

</td><td>Samples MOSI on SCLK rising edge; outputs data\_valid pulse

</td></tr><tr><td>data\_register

</td><td>Synchronously latches input d into q when load = 1

</td></tr><tr><td>LEDs

</td><td>Displays the 8-bit output from the register

</td></tr></tbody></table>

</div>**Slave Blocks:** On one workstation, instantiate and configure the spi\_slave and data\_register blocks. Record a GIF showing:

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXeWeeHU8aXkSuaDJV5VrguP3Q4RN052JbCZ9FJWhOD24BMqkgu583U-04vcGMJXKTDASMod_xFpCQSWYFcNOebG8YimTos2SgCNY8As1GlpweclAGFxoDH6a-tUjZZ0m0nJ4rcZR_PgdszJx9f175o?key=jf2tbarAhI5qOMz-WeYmBR_q)

**Master Block:** On a separate workstation, instantiate and configure the spi\_master block. Record a GIF that demonstrates:

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXcCS4JAroC6PfEvxjf8mpEggZPYwAEpYWWRPXM2sMmu25TXGolkRLlD2Q_bZYdxL7szK9OlO3EY6wLhkqYarBPOp3IRVdAvcP2MJCuN0Mhi1-lQapnihwPOv43EjuL3qsYNM9uw_nlL8QziijRshD4?key=jf2tbarAhI5qOMz-WeYmBR_q)

# Top-Level Connections

In this project, the FPGA Master and FPGA Slave are interconnected as follows:

- **Common signals (both FPGAs):**
- clk: system clock
- rst\_n: active-low reset

- **Master → Slave connections:**
- sclk: serial clock
- mosi: master data output
- cs\_n: chip select (active-low)


![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXdukq4PYiR_wBCvPpZrZseAO5lKHCBmfUXbWeNLt9IClH00JyUmgCGDJLql3krgKQgvPC3SVPfqepT7I9hY2Qo8xllLOnRhcP06xf0V7OAVZWjrFWJDqbdHCVSy3WMnp3Q7XR3s-JaXe3xMalx2OWk?key=jf2tbarAhI5qOMz-WeYmBR_q)

- **Slave internal connections:**
- data\_valid → load input of data\_register
- data\_out\[7:0\] → d input of data\_register

- **Final output:**
- data\_register.q\[7:0\] → LEDs on the board


![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXeQ6tLcRDeY09NDh2dFfr3lJ18YpTw8cHul4H5I5FvTDI3r0ma0SndK_uSscZV1mGrz0B5YyVDhIL8o_3zlQsxOY083_YMQECrBBqzLIT5h0AP44Ne0Zlcftt3jGTQfGMHN02r7gpxZft0LY5VeNA?key=jf2tbarAhI5qOMz-WeYmBR_q)

# Simulation

1\. Go to the Simulate tab and select Advanced Simulation.

2\. Run Iverilog.

3\. Check the console for compilation errors.

4\. In the waveform viewer, monitor key signals:

- spi\_master.byte\_counter
- spi\_slave.shift\_reg
- data\_valid
- data\_out

5\. Confirm that on each deassertion of CS\_n, eight bits are received, data\_valid pulses, and data\_out matches the transmitted byte.

# FPGA Synthesis and Programming

1\. Open the Synthesize tab and click Start Synthesis.

2\. Wait until all synthesis items turn green.

3\. Connect your FPGA board via USB.

4\. Select the appropriate programming port.

5\. Click Flashing to program the master and slave bitstreams.

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXcdOd5tt1bHSBOaAwfwlo3wTYuSgQh5F-1ZzSn3muIFA_KlbCEJspi6Ladu0uI2mxeRu69uds0SRRyuhSB5kx17tXwesaT206BXec7DkPWgBpBazrla5uGoCc1p8W992AzGxtGrEwN9cesrV-uwgmY?key=jf2tbarAhI5qOMz-WeYmBR_q)

# Hardware Validation

1\. Power on both FPGAs.

2\. Observe the slave’s LEDs—they should display the incrementing byte sent by the master.

3\. If the LEDs do not update correctly:

- Verify the polarity and wiring of rst\_n.
- Check connections for sclk, mosi, and cs\_n between the boards.
- Adjust the CLK\_DIV parameter in spi\_master for proper timing.

4\. (Optional) Use a logic analyzer to probe the SPI lines and verify signal integrity.

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXflGaqMvWNOry3dM8sI0FeHMwhN6nazQZ0M8CWVtxBCXLMjjxr0q-9YyFj8tUS6pMsTsELsT70C9PWhvGoNDAaqM183fmLyUdBlP0NvNv_Dt66xb1lijaBe5ffirMEp124yyn_RHURVEVSc4rLN3g?key=jf2tbarAhI5qOMz-WeYmBR_q)

# Wrapping Up

Congratulations! You have developed a complete SPI communication project using the ChipInventor platform.

Now that you understand the SPI protocol, you can expand this knowledge and implement communication with other sensors and devices.