# UART Protocol

# Understanding the UART Protocol

UART (Universal Asynchronous Receiver-Transmitter) is a widely used asynchronous serial communication protocol for exchanging data between devices, such as FPGAs and computers.

Unlike synchronous protocols, UART does not use a shared clock signal. Instead, data is sent at a predefined transmission rate (baud rate) agreed upon by both devices. Each transmitted byte includes:

- **1 start bit**
- **8 data bits**
- **1 stop bit**

During transmission, the data is sent bit by bit through the TX (transmit) line, while the receiving device reads these bits from the RX (receive) line, synchronizing with the established timing.

Below is a placeholder for an image that illustrates how UART works (start bit, data bits, stop bit, idle state, etc.).![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXd5bmlIa3u48IMnmnpwF6Px9kA8UUh83NRUwvtytNiTNLBaxXkZU3nd3ce1CnzsUGB_3k9HJFRoijvaCJLSt0b2aKf5WrYEFC1pWOw1w29KGNB_qttxy3FQcKmgE9G_De5Y0UsYqYacriGsBQNSjR4?key=YzRfqNURUUSYVoA93cajgSs0)

# Creating Your Project in ChipInventor

In this tutorial, you will create a serial communication system using UART with three main blocks: uart\_rx, uart\_logic\_const, and uart\_tx. When a character is received via UART, the system compares it with a predefined value and toggles an LED if it matches.

##### **Step-by-Step:**

1\. Open **ChipInventor**.

2\. Click on "**New Project**".

3\. Fill in the fields as follows:

- **Name:** UART Communication FPGA
- **Description:** UART system with RX, logic comparison, and TX
- **Type:** FPGA

4\. Click "**Create**".

# Blocks Used in the Project

The project uses the following blocks based on the provided Verilog modules:

- **uart\_rx:** Responsible for receiving data from the UART port and indicating when a byte has been completely received.
- **uart\_logic\_const:** Compares the received byte with a predefined character and toggles an LED state.
- **uart\_tx:** Sends data via the UART serial port.
- **Input/Output Pins:**
- clk: Main system clock
- uart\_rx: UART data input
- uart\_tx: UART data output
- b0: Reset button
- led0: Indicator LED


**![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXdBOW933JDTSW5pd4F1LqwnInb6-90ERP037T4p2eaVfKWFZ1oLJCnfqJBYTpmy8w5-wSEGK9EBID6hZIlMaqI42Y1R_mYqfICklaicaDxEZWAHCW6gUzPQeaEhaVBRe4i2--Wmf75CqyAQBjytqBM?key=YzRfqNURUUSYVoA93cajgSs0)**

# Connecting the Blocks

Assemble the project with the following configuration:

##### **uart\_rx Block**

- **Inputs:**
    - clk → system clock
    - uartRx → UART input pin
- **Outputs**: 
    - rxByte → connects to the logic block
    - byteReady → connects to both the logic block and uart\_tx

##### **uart\_logic\_const Block**

- **Inputs**: 
    - clk → system clock
    - rxByte → from rxByte output of uart\_rx
    - byteReady → from byteReady output of uart\_rx
    - compareChar → constant value (e.g., 8’h61 = 'a')
- **Output**: 
    - signal → connects to LED (led0)

##### **uart\_tx Block**

- **Inputs:**
    - clk → clock
    - reset → button (b0)
    - tx\_data → receives rxByte from uart\_rx
    - tx\_data\_valid → receives byteReady from uart\_rx
- **Output**: 
    - tx\_pin → connects to the UART TX output pin
    - tx\_data\_ready → not used in this simple project

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXcLl-qV9QUU46bIhFgQ9xhd3ZKdP-J0SiwjRH15r_-klDmRGc14tb_qRgZec3oyGqrXpf8jGePBquCH7SB8eq9lTKvHjM5OQIo9fOAWw-T8IAdlfYimdFPoEfPLd-iiAyKeX5L-6ssvTx8HUMMTFYI?key=YzRfqNURUUSYVoA93cajgSs0)

**Final Connections:**

<div align="left" dir="ltr" id="bkmrk-block%2Fpin-connection"><table border="1" class="align-center" style="border-collapse: collapse; width: 52.7381%;"><colgroup><col style="width: 29.3495%;"></col><col style="width: 70.5976%;"></col></colgroup><thead><tr><td>Block/Pin

</td><td>Connection

</td></tr></thead><tbody><tr><td>clk

</td><td>All blocks

</td></tr><tr><td>uart\_rx

</td><td>UART RX input

</td></tr><tr><td>uart\_tx

</td><td>UART TX output

</td></tr><tr><td>b0

</td><td>Reset signal for uart\_tx

</td></tr><tr><td>led0

</td><td>Output from signal of uart\_logic\_const

</td></tr></tbody></table>

</div>

# Project Simulation

1. Go to the Simulate tab in the top menu.
2. Select Advanced Simulation.
3. Click on Run Iverilog to compile and simulate.
4. Check if the simulation runs without errors.

- If errors occur, review the block connections as described.

# FPGA Synthesis and Programming

**Once the simulation is validated:**

1\. Go to the Synthesize tab.

2\. Click Start Synthesis.

3\. Connect your FPGA to the computer via USB.

4\. Select the correct serial port (usually labeled “Enhanced”).

5\. Click Flashing to program the FPGA.

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXcSeiDg9NDTE8_bVygKRAV__Ox_qMJZuIG-UZNMjy618PFPSqQhKHmhD3H8e94a8DqzErhsztredgvIbX4F15UiKkEX0VuRxLAeduieMAqEoA_Rtz2CWsBwW8Cub-g2dJRlLJ4woydF8_PJo23gA5o?key=YzRfqNURUUSYVoA93cajgSs0)

# Hardware Validation

1\. Access the **Main** tab.

2\. Click on **Serial Console**.

3\. Set the baud rate to **115200**.

4\. Send a character via the serial terminal.

- If the character matches the predefined value (8’h61), the LED should toggle.
- The same character will also be sent back through the TX pin (echo).

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXeh5Q7OrAEx5MbNAlQd2myMEGVNmPRvXPDIGwzZQcv4eeClNTQZuXRT2pFKrT8ywEaTyiww7EuBwu55jT08zOL29GzlplJdhtZps1x2nBNwwfTcjZPk9KPtHTFdzpvyN8XaYT4FKjpDWRHoHTFRNw?key=YzRfqNURUUSYVoA93cajgSs0)

![](https://lh7-rt.googleusercontent.com/docsz/AD_4nXdvWDB61XOqHpwdRjNbe2HC_wU_N4Bp4nJMuGUYtnWEvTPs66Lju3fWgX_w2F9uDOU3UQstGuUR5YOLzX2kgKczJ9OlVJCP73_cDu_0nM7orUMkzdvL10b8Edd9HRCq8qVA3W15oBdbBKuv_HE7jZs?key=YzRfqNURUUSYVoA93cajgSs0)

# Wrapping Up

Congratulations! You’ve implemented a complete UART system with receiving, comparison, and data echo. This practice reinforces your understanding of serial communication, logical comparison, and module integration in FPGA using ChipInventor.

Try experimenting with different characters, adding more conditions, or expanding the system with multiple LEDs and control commands!