Simulation Stage

Before programming the FPGA, verify that your project behaves as intended.

1. Go to the Simulate tab in the top menu of ChipInventor.

2. Select Advanced Simulation or Dynamic Simulation,Simulation, depending on your needs.

3. Click Run Iverilog (for advanced simulations), and check that there is no error.

[Advanced Simulation]

4. Monitor key signals (for advanced simulation - Create VCD)VCD):

• • Encoder counter (w_7) changing according to quadA and quadB.

  • Setpoint pulses (w_3) when pressing the key.

  • Error (w_5), gains (w_6, w_13), and resulting values (w_8).

  • Duty cycle (w_14) and PWM signal (w_11).

  • Motor direction (through w_10 and outputs IO69, IO68).

[VCD Simulation]

If you get compilation errors or unexpected behavior, review the module connections and re-run the simulation until the results match your expectations.