Simulation

1. Go to the Simulate tab and select Advanced Simulation.

2. Run Iverilog.

3. Check the console for compilation errors.

4. In the waveform viewer, monitor key signals:

• spi_master.byte_counter
• spi_slave.shift_reg
• data_valid
• data_out

5. Confirm that on each deassertion of CS_n, eight bits are received, data_valid pulses, and data_out matches the transmitted byte.