Top-Level Connections

In this project, the FPGA Master and FPGA Slave are interconnected as follows:

• Common signals (both FPGAs):

• clk: system clock

• rst_n: active-low reset

• Master → Slave connections:

• sclk: serial clock

• mosi: master data output

• cs_n: chip select (active-low)

• Slave internal connections:

• data_valid → load input of data_register

• data_out[7:0] → d input of data_register

• Final output:

• data_register.q[7:0] → LEDs on the board