Project Simulation

Before programming your FPGA board, validate the RISC-V operation in simulation:

1. Click Simulate at the top of the ChipInventor interface.

2. Choose Advanced Simulation to see detailed waveforms.

3. Click Menu → Run Iverilog.

4. If there are no errors, observe key signals such as:

• pc: should advance each cycle (unless there is a stall).
• instruction: the instruction read from imem.
• alu_result_Exec: ALU results.
• mem_write_Mem and write_data: enabling and value of writes to memory.
• read_data: data returned by memory on a load operation.

5. If you encounter errors, review connections, bus widths, or clock/reset parameters.

6. Repeat simulation until everything behaves as expected.