Understanding the Project and the Blocks Used

Below are the main blocks that make up our RISC-V project, in a structure similar to the previous tutorials.

franken_riscv

The central processor, responsible for fetching, decoding, and executing instructions, as well as handling memory/register reads and writes.

• Main Inputs:

• clk: the system clock

• reset: global reset signal

• instruction: the instruction from the instruction memory (imem)

• read_data: data returned by the data memory (blockram)

• Main Outputs:

• pc: the program counter value

• mem_write_Mem: enables writes to data memory

• write_data: the value to be written to data memory

• alu_result_Exec: result of arithmetic/logic operations

• reg_write_WB: enables writes to the register file

imem

• • Function: The instruction memory for RISC-V.

  • Behavior: Receives pc and returns the corresponding instruction on instr.
    
    

blockram

• • Function: Data memory for load and store operations.

  • Behavior: Used by the processor to read (read_data) or write (write_data) data at the address (addr) provided by the ALU.
    
    

register

• • Function: The RISC-V register file (x0 to x31).

  • Behavior: Reads or writes values based on control signals (reg_write_WB, RS1, RS2, RD).
    
    

inverterC

• • Function: Inverts the input signal (commonly used for generating an active-low reset).
    
    

one_hz_clock

• • Function: Generates a 1 Hz clock for slowing down and making the system operation more observable (optional).
    
    

screen (optional)

• • Function: Displays data on a screen, useful for seeing register values or debug messages.
    
    

textEngine (optional)

• • Function: Converts characters into bitmaps to be displayed by screen.
    
    

mux4_8, bus_to_wires, bus_to_bus_4_5, stringbyte, alu_decoder, and others

• • Function: Support modules for signal routing, bus multiplexing, and instruction decoding.
    
    

Finally, a top module integrates all these components, mapping outputs to physical pins.